ARM EN0-001 Exam - Questions and Answers

Question 1

A simple system comprises of the following memory map:

Flash - 0x0 to 0x7FFF -

RAM - 0x10000 to 0X17FFF -
When conforming to the ABI, which of the following is a suitable initial value for the stack pointer?

A. Top address of RAM (0x18000)
B. Top address of flash (0x8000)
C. Bottom address of RAM (0x10000)
D. Bottom address of flash (0x0000)

Answer : A

Question 2

Assume a Big-Endian (BE) memory system with the following memory contents.

Byte Address Contents -
0x100 0x11
0x101 0x22
0x102 0x33
0x103 0x44
If R5 = 0x100, what are the contents of R4 after performing the following operation?
LDR R4, [R5]

A. 0x11223344
B. 0x44332211
C. 0x22114433
D. 0x33441122

Answer : A

Question 3

An Advanced SIMD intrinsic has the prototype:
uint8xl6x2_t vld2q_u8 (uint8_t const * ptr);
How many bytes does this intrinsic load from memory?

A. 2
B. 16
C. 32
D. 256

Answer : C

Question 4

When an ARMv7-A MPCore system is in SMP mode, which of the following TWO operations can the processor handle automatically? (Choose two)

A. Coherency management between all L1 data caches
B. Broadcast of some inner-shared cache and TLB maintenance operations
C. Broadcast of some outer-shared cache and TLB maintenance operations
D. Coherency management between all L1 instruction caches
E. Coherency management between all external caches

Answer : AB

Question 5

In an ARMv7-A processor with Security Extensions, which of the following mechanisms best describes the way Secure memory is protected from access by software running in a
Non-secure privileged mode?

A. The memory system has visibility of the security status of all accesses, and will reject all Non-secure accesses to Secure memory
B. Secure memory contents are encrypted, and cannot be decrypted by Non-secure software
C. The level 2 cache controller blocks all accesses to Secure memory when the SCR.NS bit of the processor is set
D. The MMU generates an abort on accesses to Secure memory performed by Non-secure software

Answer : A

Question 6

Which TWO of the following interrupt types does a Generic Interrupt Controller (GIC) support? (Choose two)

A. Interrupt from a private peripheral to a processor
B. Interrupt from a processor to a private peripheral
C. Interrupt from a shared peripheral to a processor
D. Interrupt from a processor to a shared peripheral
E. Interrupt from a private peripheral to a shared peripheral
F. Interrupt from a shared peripheral to a private peripheral

Answer : AC

Question 7

The effect of clicking the Stop button in a debugger is to:

A. Put the processor(s) into debug state.
B. Force the processor to execute a BKPT instruction
C. Hold the processor in a Reset condition
D. Re-initialize the memory contents.

Answer : A

Question 8

When using an Operating System, which of the following operations can NOT typically be done by user processes?

A. Reading the link register (R14)
B. Reading data from the user stack
C. Changing from ARM state to Thumb state
D. Changing the interrupt mask bits (A, I, F) in the CPSR

Answer : D

Question 9

Processors which implement the ARMv7-A architecture can be configured to allow unaligned memory access. Unaligned accesses have a number of advantages, disadvantages, and limitations.
Which TWO of the following statements are true? (Choose two)

A. Unaligned accesses may take more cycles to execute than aligned accesses
B. Unaligned loads and stores are necessary for accessing fields in packed structures
C. A program compiled using unaligned accesses can be safely executed on all ARMv7-A devices
D. If the relevant control register setting is enabled all loads and stores can function from unaligned addresses
E. Unaligned accesses can only be made to Normal memory

Answer : AE

Question 10

When should an ISB instruction be used?

A. When executing a long branch
B. When clearing the branch predictor caches
C. When reading a register from a coprocessor
D. When returning from an exception handler

Answer : B

Question 11

In an experiment, the time taken for an application to complete a given task is measured using a stopwatch. Which THREE of the following make up the total time? (Choose three)

A. The time spent waiting for I/O operations
B. The time taken to download the program via the debugger
C. The time taken for memory accesses
D. The time taken for the CPU to execute instructions
E. The time taken to compile the source code
F. The time taken to perform instruction tracing

Answer : ACD

Question 12

In general, when programming in C, stack accesses will be reduced by:

A. Disabling inlining.
B. Never passing more than four parameters in function calls.
C. Declaring automatic variables as "packed".
D. Configuring the compiler to optimize for space.

Answer : B

Question 13

Which of these instructions is a correct translation of the body of function f? struct T { char a; int b; }; int f(struct T *p) { return p->b; }

A. LDR r0, [r0], #1
B. LDR r0, [r0]. #4
C. LDR r0, [r0.#1]
D. LDR r0, [r0. #4]

Answer : D

Question 14

When using a Generic Interrupt Controller (GIC), how does code cause a software- generated interrupt?

A. By executing an SGI instruction
B. By writing to a register in the GIC
C. By writing to the F bit in the CPSR
D. By writing to the I bit in the CPSR

Answer : B

Question 15

The ARMv7-A virtual memory management system supports 32-bit (short) and 64-bit (long) page table descriptors. The sizes of a small page in a short descriptor and a small page in a long descriptor are:

A. 1 KB and 4KB respectively
B. 4KB and 4KB respectively
C. 4KB and 16KB respectively
D. 16KB and 16KB respectively

Answer : B

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